We are looking for a Wireless DSP / PHY Firmware Engineer to join our CSM Firmware team in Espoo and contribute to the development of next‑generation wireless modem and radio systems

In this role, you will design, implement, and optimize PHY‑layer firmware algorithms for advanced multi‑antenna wireless systems, taking features from algorithm concept through on‑target validation You will work closely with system, VLSI, RF, and test teams, and play a key role in translating wireless theory into robust, high‑performance firmware running on real hardware.

Key Responsibilities

• Define firmware architecture for advanced wireless and PHY features

• Implement and optimize PHY‑layer DSP algorithms (TX/RX chains, estimation, equalization, beamforming, etc.)

• Translate system‑level and algorithmic requirements into production‑ready firmware

• Drive FW integration and bring‑up on target hardware, in close collaboration with system and HW teams

• Analyze performance, latency, and resource usage; identify bottlenecks and propose design improvements

• Debug and resolve complex performance, robustness, and reliability issues

• Act as a technical focal point for firmware topics across system, HW, RF, and validation teams

Required Qualifications

• 3+ years of hands‑on experience in wireless communications and/or DSP algorithm implementation

• Strong experience with DSP or embedded firmware development

• Solid background in modem and PHY‑layer processing

• Experience defining end‑to‑end firmware design flows and working across FW, HW, and system teams

• Familiarity with at least one wireless standard (e.g. 5G NR, LTE, Wi‑Fi)

• Proficiency in C/C++ for performance‑critical embedded or DSP code

• Strong analytical and debugging skills, with the ability to explain complex FW behavior clearly

• Bachelor’s degree in Electrical Engineering or a related field

Preferred Qualifications

• Hands‑on experience in PHY / modem firmware for cellular systems

• Experience with fixed‑point implementations, real‑time constraints, and DSP optimization

• Exposure to multi‑antenna systems (MIMO, beamforming, precoding, combining)

• Experience translating algorithms into production firmware, HW accelerators, or RTL

• Familiarity with on‑target debugging, trace tools, and performance analysis

• Master’s or PhD in Electrical Engineering or a related field

• Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.

• 3+ years of ASIC design, verification, validation, integration, or related work experience.
• 2 + years of experience with architecture and design tools
• 2 + years of experience with scripting tools and programming languages

• 2 + years of experience with design verification methods.

Principal Duties & Responsibilities:

• Applies ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products.

• Creates architectures, circuit specifications, logic designs, and/or system simulations based on system-level requirements.

• Collaborates across teams (e.g., software architecture, hardware architecture) to develop and execute an implementation strategy that meets system requirements and customer needs.

• Evaluates all aspects of process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow.

• Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable architecture and design of an individual block/SoC or IC Package.

• Writes detailed technical documentation for EDA/IP/ASIC projects.

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