We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years deep in ASIC design and verification, and somewhere along the way you realized that the most satisfying part of the work is not just getting the design right, it is helping someone else get their design right. You are the engineer who actually enjoys the call when a customer hits a wall before tapeout. Not because you love chaos, but because you know how to isolate the problem, ask the right questions, and get them unstuck.

You have worked across enough of the ASIC flow that you can speak synthesis in the morning, debug a CDC issue after lunch, and walk a customer through STA constraints before you leave. USB protocols are not abstract specs to you. You have lived with them long enough to know where integration usually breaks and what questions to ask during bring-up that save weeks later.

What You'll Be Doing

• Provide technical support to customers integrating DesignWare USB Mixed Signal PHY IP, from initial integration through silicon bring-up and debug
• Troubleshoot customer issues across synthesis, static timing analysis, design-for-test, and clock domain crossing
• Guide customers through USB 2.0, USB 3.x, and Type-C protocol implementation and design tradeoffs
• Collaborate with Synopsys R&D and product teams to escalate complex issues and feed customer requirements back into the roadmap
• Deliver technical presentations and integration best practices to customer engineering teams during design reviews
• Travel occasionally to customer sites across Korea and the region to support critical milestones

The Impact You Will Have

• Enable customer success on high-stakes tapeouts by resolving integration issues that would otherwise delay schedules
• Reduce time-to-silicon for customers by providing clear, actionable guidance during critical design phases
• Build deep technical relationships with leading semiconductor companies in Korea as their trusted advisor
• Shape future IP releases by channeling real customer pain points back to the product team
• Expand Synopsys footprint in customer accounts through technical depth and responsiveness
• Help customers achieve first-pass silicon success, directly impacting their product launches and our market reputation

What You'll Need

• Bachelor's or Master's in Electrical Engineering or Computer Engineering with 8+ years of ASIC design or verification experience
• Strong working knowledge of synthesis, static timing analysis, design-for-test, and clock domain crossing
• Ability to work independently and drive issues to resolution in customer-driven, ambiguous situations
• Excellent communication skills in Korean and English, able to explain complex concepts clearly
• Experience with USB 2.0, USB 3.x protocols, or Type-C is a strong plus
• Willingness to travel occasionally within Korea and the region

Who You Are

• You can take a vague customer complaint and within two questions know whether it is a constraint issue, integration problem, or something else
• You are comfortable saying "I do not know, but I will find out" and then actually following through
• You know when to pull in the right specialist from R&D and how to frame the problem so they can help
• You can explain a complex tradeoff to a customer architect in two sentences without losing the nuance
• You see customer edge cases as opportunities to improve, not complaints to deflect

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.