
Les systèmes sur puce (SoC) modernes intègrent plusieurs processeurs, accélérateurs matériels, sous-systèmes mémoire et interconnexions complexes. Avant même la disponibilité complète du matériel, il est essentiel d'évaluer les performances du système afin de vérifier que les objectifs d'architecture sont atteints en termes de débit, bande passante et latence.
L'objectif de ce stage est de développer un modèle de performance permettant de représenter différents composants du SoC (cœurs processeurs, accélérateurs, mémoires, interconnexions) et de simuler leur comportement sous différentes configurations et charges de travail.
Modern System-on-Chip (SoC) devices integrate multiple processing cores, hardware accelerators, memory subsystems, and complex interconnect architectures. Early performance assessment is critical to ensure that architectural targets are met before the complete hardware implementation becomes available.
The objective of this internship is to develop a performance modeling framework capable of representing different SoC components (CPU cores, accelerators, memories, and interconnects) and simulating their behavior under various configurations and workloads.
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