As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.

As a QualcommHW SoCEngineer, you will define, model, design (digital and/or analog),optimize, verify,validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products.Qualcomm Engineers collaborate with cross-functional groups todetermineproduct execution path.

We are seeking a seasoned Staff / Sr Staff Physical Design Engineer to provide technical leadership across block-level, die-level and chip-level physical implementation on advanced FinFET nodes. You will define and own the backend design methodology, champion Agentic AI integration into the PD flow, and mentor engineers across the team while interfacing directly with foundry, EDA vendors, and executive stakeholders.

Preferred Qualifications:

• Master's degree in ElectricalElectronic Engineering, Computer Engineering, or Computer Sciencewith 12+ years of experience

• Deepexpertisein full-chip and block-levelfloorplanning,design implementationthrough place and route,clock architecture, STA,Timing / Power closure, andPhysical sign-off;

• Experience with power optimization (DVFS, multi-Vt, power domains, UPF/CPF)

• Expertproficiencyin EDA toolsfromCadence/SynopsysMentor/Ansys

• AdvancedShell,PythonandTclscriptingability to architect large-scale PD automation frameworks and flow infrastructure

• Proven experience in flow development: designing, implementing, and owning end-to-end backend design flows at team or organization level

• Demonstrated experience or vision for applying Agentic AI methodologies to EDA challengesautonomous agents, AI-driven optimization, LLM-assisted debugging

• Strong communicationskillsability to presentmethodologydecisions, risk assessments, andtapeoutreadiness to senior management

Principal Duties & Responsibilities:

• Leverages advanced ASIC knowledge and experience to define, model, design (digital,analogand/ormix signal),optimize, verify, validate andimplementIP (block/SoC) development for a variety of high performance, high quality, low power products.

• Participates in orleadsthedesignimplementation of advanced design rules and processes for electronic hardware, equipment, and/or integrated circuitry.

• Conductshighly complexsimulations and analyses of designs as well as implements designs with the best power, performance, and area.

• Collaborates with cross-functional teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.

• Evaluates all aspects of complex process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow.

• Utilizes tools/applications (e.g., RTL to GDS Flow) to execute and enable advanced architecture and design of multiple complex blocks/SoC or IC Packages.

• Writes and reviews detailed technical documentation for complex EDA/IP/ASIC projects.

Level of Responsibility:

• Works independently with minimal supervision.

• Provides supervision/guidance to other team members.

• Decision-making is significant in nature and affects work beyond immediate workgroup

• Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc.

• Has a moderate amount of influence over key organizational decisions (e.g.,is consultedby senior leadership to make key decisions).

• Tasks do not have defined steps; planning, problem-solving, and prioritization must occur to complete the tasks effectively.