Job Description

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more atwww.silabs.com

What we’re looking for:

It is if you are a highly motivated, self-driven, talented Engineer with demonstrated knowledge of the IC design flow, all the way from initial idea to implementation and manufacturing.

Engineers inquiring about this position should be familiar with digital implementation tools with focus on back-end implementation tasks like, floor-planning, clock-tree-synthesis, power-planning, timing and routing optimization as well as physical ECO implementation.
High level of scripting in TCL, perl and python is required to maintain and develop implementation flows.

Successful candidates will have excellent written and oral communication skills and will be comfortable explaining technical concepts to a wide range of audiences, including senior engineering leaders.

The candidate will be a technical contributor as part of a digital engineering team implementing highly integrated mixed signal SoC’s for IoT products performing back-end implementation using deep sub micron technology.

• Block and chip level floorplanning, pre-wire and timing-optimization tasks

• Data preparation of IP like analog and RF macros.

• Detailed place and route for both block macros and chip level, including clock-tree-synthesis, power routing, timing driven placement and routing, signal integrity analysis, and design for yield techniques

• Generation of detailed parasitic information

• Static and Dynamic rail analysis

• Signoff Static Timing Analysis

• Physical verification, including LVS and DRC

• Maintenance of PnR flows

• Development of new flow features and tool evaluations

Skills you’ll need:

• Strong knowledge of engineering fundamentals

• Knowledge of System-On-Chip or ASIC design, and understanding of SoC or ASIC tools/flows
  Advanced design implementation skills: synthesis, floorplanning, clock tree synthesis, power routing and analysis, timing driven place and route, signal integrity analysis, parasitic generation, static timing analysis, physical verification

• Advanced knowledge of low power flows, including voltage/power domains, power shutoff, retention.

• Advanced knowledge of CMOS fabrication processes

• Understanding of design for test techniques, including scan insertion, ATPG, Memory BIST, JTAG

• Knowledge of scripting/language (perl, shell, tcl, python)

• Familiarity with Quality systems and procedures

• Excellent written and verbal communication skills

Education:

• MS in Electrical Engineering, or equivalent

Benefits & Perks:

Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun.

• Medical and dental insurance coverage including spouse and child(ren)

• Bi yearly health screening and flu vaccination

• Office location is above Tai Seng MRT station

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Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.