Job Description

Sense the power of light

The ams OSRAM Group is a global leader in innovative light and sensor solutions. With more than 110 years of industry experience, we combine engineering excellence and global manufacturing with a passion for cutting-edge innovation enabling transformative advancements in the automotive, industrial, medical, and consumer industries. “Sense the power of light” – our success is based on the deep understanding of the potential of light and distinct portfolio of emitter and sensor technologies. Around 19,700 employees worldwide drive innovations alongside societal megatrends.
Find out more about us on https://ams-osram.com

The CSA division supplies sensors that bridge the gap between the world we live in and the digital world of machines. By converting physical signals - heartbeats, sounds, light waves - into data, we enable robots, cars and other devices to interact with people and improve our world. What drives CSA is a relentless desire to contribute to technology and have a meaningful impact on the world. This business thrives on solving complex problems and partnering with global leaders at the forefront of technological advancement. Our goal: to push the boundaries of sensor technology and empower innovators to make the world smarter, healthier and happier.

Your new responsibilities

• Close cooperation with the whole product development team (NPI, Project Management, Design, Apps, Etc.) to ensure testability of IC products in a very early product design phase. This may include but not limited to influencing the product design engineer to consider design for test (DFT) considerations such as developing the best test concepts and practices for Wafer Level and Package Level tests.
• Responsible in the definition and development of a new product test solution taking into account device datasheet requirements, development cost, lead time and test coverage. This test solution will include mass volume wafer level test and Package Final test (Ex. Load board, probe card, Etc.)
• Acts as the overall lead for all back-end manufacturing development needs. This may include project planning, providing quotes for product test times, HW/SW development, debug and characterization.
• Responsible for the pre-production cycle of new product development. Tasks include the creation of HW and SW both for Final Test and Wafer sort. Debug and qualification of all test parameters as per datasheet requirements thereby ensuring very good test coverage, a repeatable, stable and quality driven test solution. As part of the process, you will transfer all product know-how that was gained and encountered during the development phase. This may include knowledge transfer activities such as trainings, transfer of technical documentation and solutions, Etc.

Who we are looking for

• Bachelor's Degree in the areas of Electrical, Electronics, Microelectronics & Measurement Engineering. Master’s Degree is a plus
• Minimum 3-5 years test development, SW/HW application, Test Validation work experience in the semiconductor industry with a strong technical background and exposure on IC testing of Power Management, Mixed Signal, Automotive, Industrial, Medical and Sensor IC products.
• Hands-on experience with deep hardware and software coding and debug knowledge techniques using ATE Machines such LTX-EX and Diamond-X. Familiarity and understanding in the usage of ATE SW tools such as Unison, Envision, Cadence, Pattern tool, Capture tool and C++ coding is a must.
• Deep understanding and experience with high level structured programming languages such as Python and C++.
• Strong knowledge and understanding of HW circuit design and PCB design rules (Ex. Placement of components, groundings, separation of high and low speed signals, Etc.). Familiarity with the usage of PCB software (Ex. Altium, Etc.) and deep knowledge in HW circuit simulation techniques is a plus.
• Familiarity and experience in digital pattern debug and fail pattern vector code identification. Must have a clear understanding of digital pattern characterization techniques such as force pattern fail check & shmoo plot analysis.

Please contact Soi Kim Kee for further information via suki.kee@ams-osram.com or +65 () 62402395