We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

We are seeking a highly motivated and innovative Digital Verification Engineer with a strong theoretical and practical foundation in high‑speed data recovery circuits.

As a key member of our highly experienced mixed‑signal design team, you will contribute to the verification of current and next‑generation products, including Backplane Ethernet, PCIe, SATA, USB 2/3, DisplayPort, MIPI MPHY, C‑PHY and D‑PHY SerDes solutions.

This role offers an excellent opportunity to collaborate with an expert group of digital and mixed‑signal engineers responsible for delivering high‑performance mixed‑signal designs—from test plan creation and testbench development to RTL/GLS regressions and full coverage closure.

What You'll Be Doing

• Develop test plans for mixed-signal SerDes IP including MIPI C-PHY and D-PHY
• Build and extend UVM testbenches using constraint-random methodologies, modifying scoreboards, agents, and sequences to support new product features
• Write advanced System Verilog tests that validate digital and mixed-signal interaction across RTL and gate-level simulations
• Run RTL and GLS regressions, analyze failures, debug root causes, and work with design teams to resolve issues
• Drive code and functional coverage closure,identifyinguntested scenarios and writing directed or constrained-random tests to fill gaps
• Explore and prototype AI-driven verification techniques to improve test generation, coverage analysis, or regression triage
• Collaborate with analog, digital, and architecture teams to ensure verification aligns with design intent and product requirements

The Impact You Will Have

• Your test plans will define verification completeness for high-speed SerDes IP used in automotive, mobile, and data center applications
• The testbenches you build will enable faster verification cycles and higher confidence attapeoutfor current and next-generation products
• Your regression analysis and debug work will catch critical issues before silicon, reducing costlyrespinsand schedule delays
• The coverage strategies you implement will ensure that corner cases are tested and verified, not assumed
• Your collaboration with mixed-signal design teams will improve the quality and robustness of IP delivered to customers

• The AI verification techniques you explore will shape how the team approaches automation and efficiency in future projects
• Your work will directly contribute to the success of Synopsys Silicon IP products that power billions of devices worldwide

What You'll Need

• 5+ years of ASIC verification experience, with a focus on digital or mixed-signal IP
• Strong hands-on experience writing complexSystemVerilogtestcases for functional verification
• Proven experience developing UVM-basedtestbenches, including building ormodifyingagents, scoreboards, and sequences
• Proficiencywith Python or other scripting languages for automation, regression management, or post-processing
• Experience with high-speed interface protocols such asMIPI,PCIe, USB, SATA, Ethernet,orDisplayPortisa strong plus
• Familiarity with RTL and gate-level simulation flows, including coverage analysis and regression debug
• Experience with mixed-signal verification or working closely with Co-sim teams is a plus

Who You Are

• You can look at a test plan and immediately spot what is missing, whether it is a corner case, a protocol edge condition, or a coverage gap
• When a regression fails, you do not wait for someone else to triage it. You dig into waveforms, logs, and assertions until you understand what broke and why
• You are comfortable working across teams. You can explain a verification issue toadigitaldesigner or a coverage strategy to a project lead without losing clarity
• You take ownership of yourtestbenches. If something is broken, inefficient, or hard tomaintain, you fix it rather than work around it
• You are organized enough to manage multiple verification tasks in parallel, from writing new tests to closing coverage to debugging gate-level issues
• You are curious about new methods. You do not need AI verification to be fully proven before you are willing to experiment with it and see where it helps

The Team You'll Be Part Of

You will join a highly experienced mixed-signal design and verification team responsible for delivering SerDes IP across a wide range of applications. The team works on current and next-generation products, collaborating closely with digital and analog Engineers to ensure high-performance, production-ready IP. This is a team that values technical depth, collaboration, and ownership, and you will have the opportunity to work with experts who have been solving hard verification problems for years.

Rewards and Benefits