Job Description

We are seeking a highly skilled and experienced Senior/Staff DFT (Design for Test) Engineer to join our team. In this role, you will be instrumental in defining and implementing the test strategy for our complex CIS/SoC/TDDI designs. You will take ownership of the entire DFT flow, from architecture to pattern generation, ensuring the highest quality and test coverage for our products. The ideal candidate will have a proven track record of driving DFT methodology and successfully bringing multi-million-gate designs to mass production Key Responsibilities

• DFT Architecture & Planning: Develop and set the advanced DFT strategy and implementation plan based on the latest methodologies and EDA tools to achieve excellent test coverage for low and zero DPPM goals.
• DFT Implementation & Verification: Lead the implementation of DFT structures, including SCAN (full and partial), Test Compression, Memory BIST (MBIST), Logic BIST (LBIST), Boundary Scan (BSD), and JTAG. Perform verification of DFT logic and generate production-ready ATE patterns.
• Pattern Generation & Silicon Debug: Be responsible for ATPG pattern generation, simulation, and validation. Support silicon bring-up, debug test patterns on the ATE, and perform failure analysis to improve yield.
• Timing & Constraints: Generate accurate DFT timing constraints and collaborate closely with the backend design team to achieve timing closure for all test modes.
• Cross-Functional Collaboration: Work effectively with front-end design, verification, physical design, and product engineering teams to ensure testability and manufacturability are integrated throughout the design cycle.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 5+ years of hands-on experience in DFT for ASIC/SoC designs.
• Deep understanding of ASIC design flow and core DFT concepts (fault models, test coverage, etc.).
• Proven, hands-on experience in DFT implementation including SCAN insertion, ATPG, test compression, MBIST, LBIST, and Boundary Scan.
• Proficiency with industry-standard DFT tools from Synopsys (DFT Compiler, TetraMAX/ TestMAX) and/or Mentor Graphics/Siemens (Tessent platform).
• Experience with scripting languages for automation, such as Perl, TCL, or Python.
• A history of successful DFT execution on at least one complex, multi-million-gate product that reached mass production, preferably at 40nm technology node or below.
• Strong problem-solving skills, self-motivation, and excellent communication abilities for effective cross-department collaboration.
• Professional fluency in Mandarin is required due to the need to liaise with Mandarin-speaking stakeholders and team members based in China. This is essential for effective communication in meetings, documentation, and day-to-day operations.

Preferred Qualifications

• Knowledge of design synthesis and Static Timing Analysis (STA).
• Experience with low-power DFT techniques and related challenges.
• Familiarity with backend design flows and timing closure challenges is a significant plus.