Experience: 10- 15 years
Location - Bangalore/Pune/
Responsibilities:
· Complete DFT ownership of projects including:
Test architecture definition.
Identifying and implementing RTL changes for DFT.
Performing scan insertion, LEC checks, low power CLP checks.
Developing timing constraints for test mode timing closure.
Scan and ATPG for different fault models.
Boundary scan, ACJTAG, IEEE 1500 implementation and verification.
IEEE1687 (iJTAG) compliant ICL/PDL for functional manufacturing tests.
Running zero delay and timing simulations and debugging on all the above aspects.
Supporting post silicon bring up.
Interacting with customers on DFT aspects and support Marketing & Pre-Sales team.
Experience working on very high speed and low power designs.
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence’s Intelligent System Design™ strategy, are essential for the world’s leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the world’s top 100 best-managed companies. Cadence solutions offer limitless opportunities—learn more at www.cadence.com.
