Skyworks Solutions is seeking an accomplished Senior Principal Engineer to join our Analog/Mixed-Signal (AMS) Verification team. In this role, you will play a critical part in developing and advancing industry-leading AMS verification methodologies, defining scalable workflows, and selecting best-in-class tools to enable zero-defect product development while meeting competitive project schedules.

The successful candidate will perform hands-on verification of complex mixed-signal blocks, including data converters (DAC, ADC), power-on-reset circuits (POR), low-dropout regulators (LDOs), oscillators, state machines, and digital interfaces. You will derive comprehensive verification and test plans directly from product and system requirements, working closely with design teams to build deep design understanding and provide clear, actionable feedback on functionality, performance, and coverage.

This position requires a strong background in analog or mixed-signal design and/or verification, with demonstrated expertise in simulation and verification environments such as Cadence. Verification will leverage both traditional analog/mixed-signal (AMS) techniques and event-driven digital mixed-signal (DMS) methodologies. Accordingly, experience developing SystemVerilog testbenches and creating analog behavioral models using Verilog-A and SystemVerilog Real Number Modeling (RNM) is highly desirable.

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Responsibilities

Your key responsibilities will include but not be limited to:

• Perform end-to-end analog/mixed-signal verification of RF Front End Modules (FEM), from block-level through full-chip integration, leveraging schematic, behavioral, and functional views to achieve comprehensive coverage while meeting project schedules.
• Develop Verilog-A and SystemVerilog RNM behavioral models for analog and mixed-signal circuits. Perform equivalence checks to validate behavioral models match circuits.
• Define and execute verification plans derived directly from product specifications.
• Partner closely with design teams to develop deep understanding of custom circuits, providing verification feedback on functionality and performance.
• Recommend test hooks to strengthen verification and improve Design for Test (DFT).
• Review layout and floorplans to proactively identify and resolve issues.
• Continuously improve verification methodologies with an emphasis on scalability, reusability, and portability across programs.
• Own mixed-signal verification sign-off in preparation for tapeout.
• Optimize models to ensure accuracy while maintaining efficient simulation performance.
• Document modeling and verification methodologies, and promote best practices across teams and programs.
• Stay current with industry trends and emerging techniques in analog and mixed-signal modeling and verification.

Required Experience and Skills

• Requires a BS and 15 years of experience (or MS and 12 yrs or PhD and 8 yrs)
• Strong leaderships skills and ability to drive action across the organization.
• Experience with Analog/Mixed-Signal circuits, including LDOs, PORs, ADCs, Voltage-Current references and oscillators. Knowledge of RF design (LNA, PA, and Switches) is desirable.
• Knowledge of behavioral modeling of analog circuits including Verilog-A and SystemVerilog RNM.
• Experience with analog layout and knowledge of best practices for isolation, matching, noise avoidance and reliability.
• Experience with EDA tools, such as Cadence Virtuoso and ADS.
• Basic scripting language skills, such as Python, is a plus.
• Excellent communications skills with the ability to work and thrive in a team environment.