Job Description

• Lead the strategic definition and validation of AI microarchitecture design for next-generation ultra-low power, high-performance compute solutions
• Drive innovation in AI hardware/software co-design to deliver competitive advantages in power efficiency, performance, and silicon area optimization
• Serve as the technical bridge between IC design and software engineering teams, providing proven architectural specifications for implementation
• Champion design methodology improvements and best practices across the organization to enhance development velocity and product quality
• Shape the technical roadmap for AI features and capabilities that address diverse market requirements with flexible, scalable architectures

• Charter and maintain AI microarchitecture roadmap and advise on and synchronize with software team’s toolchain roadmap
• Design flexible and scalable AI architectures that can be rapidly implemented and adapted to address varying requirements across different market segments
• Develop comprehensive quantitative analysis to demonstrate and justify the technical and business merits of proposed architectural features
• Create and execute Proof-of-Concept (PoC) implementations on FPGA platforms to validate and prove that proposed architectures meet expected performance targets before handoff to implementation teams
• Provide detailed architectural specifications, interface definitions, and performance models to enable the IC Design Team to implement RTL designs with confidence
• Deliver comprehensive architectural documentation and performance requirements to enable the Software Team to implement compilers, toolchains, and drivers for the complete solution
• Collaborate closely with IC Design and Software Teams throughout the implementation phase to resolve architectural questions, clarify specifications, and ensure successful realization of the architecture
• Define, document, and roll out standardized AI Design Methodology to IC Design and Software Design teams to drive improved work efficiency and consistency
• Explore and potentially implement High-Level Synthesis (HLS) design flows using Synopsys Catapult or similar tools to accelerate design productivity

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field; PhD preferred
• 8+ years of experience in digital hardware architecture, with at least 5 years focused on AI/ML accelerator design or neural network hardware
• Proven expertise in microarchitecture definition and validation for ultra-low power applications with demonstrated track record of architectures successfully implemented in silicon
• Strong knowledge of AI/ML algorithms, neural network architectures (CNNs, RNNs, Transformers, etc.), and their hardware implementation trade-offs
• Hands-on experience with FPGA prototyping and validation using Xilinx, Intel, or similar platforms to prove architectural concepts
• Proficiency in creating detailed architectural specifications and understanding of RTL design principles to enable smooth handoff to implementation teams
• Experience defining software-visible architectural features and interfaces to enable compiler, toolchain, and driver development
• Excellent communication skills with ability to create compelling technical presentations, specifications, and documentation for executive, IC design, and software audiences
• Strong analytical and problem-solving abilities with emphasis on quantitative performance analysis, modeling, and optimization
• Experience with design methodology development and process improvement initiatives
• Familiarity with RISC-V ISA and ecosystem
• Knowledge of High-Level Synthesis tools such as Synopsys Catapult, Xilinx Vitis HLS, or Cadence Stratus (preferred but not required)
• Self-motivated with ability to work independently and drive architectural innovation from concept through validation and successful team handoff