Job Description

Job Summary

To lead a group of Junior Analysts. Deliver projects within timelines in collaboration with internal/external stakeholders

Key Responsibilities

1. Act As A Subject Matter Expert wherever required. Mentor the Junior Analysts to improve their Performance Through Feedback And Coaching. Build Product Expertise On A Large Quantity Of Diverse Products Through Thorough Research And Analysis Of Data From Multiple Channels. Provide Value Add To Business Process / Application Improvement Through Research And Analysis
2. Prepare And Develop Documentation For Tools And Project Processes To Support The Lead Trainer And Team Lead. Define Deliverables And Measures For The Project. Track Metrics At And Engagement And Individual Level And Monitor Timelines / Milestones
3. Prepare Periodic Report. Escalate And Solve Challenges With Respect To Projects In Coordination With Internal/External Stake Holders
4. Oversee A Small Group Of Project Team Who Are Responsible To Optimize Work Allocation To Maximize And Balance The Broad Set Of Goals Defined By The Team Leads

Skill Requirements

1. Expert proficiency in SoC architecture and design, with in-depth knowledge of Verilog and UVM for digital verification.
2. Excellent understanding of C and C++ development as applied to embedded systems and SoC integration.
3. Strong familiarity with RTL design, simulation tools (e.g., Synopsys VCS, Cadence), and advanced verification methodologies.
4. Advanced proficiency in developing and reviewing testbench architectures using UVM.
5. Solid experience in mentoring technical teams and driving best practices in SoC development.

Other Requirements

1. Recommended: Certified Verification Engineer (CVE) – UVM (Optional but valuable)
2. Recommended: IEEE Certified SoC Design Professional (Optional but valuable)