Cadence is searching for a Software Engineer to work on delay calculation and signal integrity (SI) analysis in Static Timing Analysis tool. Responsible for implementing and extending existing capabilities for circuit and interconnect delay and signal integrity analysis of large scale circuits, investigating techniques to improve correlation of delay/SI analysis to SPICE, and modeling of nanometer circuit effects in delay/SI analysis.
Position Requirements:
The candidate should have MS/PhD in EE/CS or related discipline, strong programming skills in C++, and deep familiarity with object-oriented programming methods. Prior knowledge and experience with multi-threaded programming, numerical analysis techniques, and delay calculation methods for nanometer circuits preferred.
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence’s Intelligent System Design™ strategy, are essential for the world’s leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the world’s top 100 best-managed companies. Cadence solutions offer limitless opportunities—learn more at www.cadence.com.
