Job Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

• The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
• Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
• The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success
• Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests
• You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.

In this job, you will be responsible for development of Formal Verification IPs in form of a Verilog design model and System Verilog Assertions for industry standard bus protocols.

This role offers front row access to the cutting-edge innovation happening in Formal Verification and an opportunity to master a variety of protocols.

Job Responsibilities :

This Job involves development of the Assertion Based Verification IPs.

• He/She should understand the designs and assertions for the formal verification.
• A fair bit of automation and scripting language like Python/TCL required in this activity.
• He/She should work as individual contributor and be a team player and need to coordinate with cross geographic teams.
• Good understanding of the verification environment and design verification methodology is required.
• Knowledge of at least one industry standard protocol (for example AHB, AXI, CHI, PCIe etc) is a MUST.
• Very strong RTL design and synthesis concepts is required.
• Strong verification concepts like understanding spec, creating test plans, adding coverage is required.
• Strong analytical and problem-solving skills required.
• Formal verification knowledge will be a plus.
• He/she should have a good working knowledge of EDA tools (Cadence/ Others) with focus towards debugging design/verification problems using these tools.

Qualifications

• BE/BTech/ME/MS/MTech in Electrical/Electronics

Experience and Technical Skills required

• 2+ years of experience in RTL design/Verification in case of BE/BTECH or master’s degree with Internship.
• Knowledge of scripting languages & Flow development is a big plus.
• Must have excellent debugging skills and ability to separate out the critical issues from trivial ones.
• Knowledge of at least one industry standard protocol (for example AHB, AXI, CHI, PCIe etc).
• Exposure to AI tools or methodologies used for verification, automation, debugging, or productivity improvement is highly desirable.

Behavioral skills required

• Must possess strong written, verbal and presentation skills.
• He/she should have good communication skills.
• Ability to establish a close working relationship with both customer peers and management.
• Explore what’s possible to get the job done, including creative use of unconventional solutions.
• Work effectively across functions and geographies.

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