Cadence Design Systems is looking for a highly motivated engineer to work with the Modus Test R&D team working on Design For Test (DFT) and Automatic Test Pattern Generation (ATPG) Software.
What You'll Be Doing
Work as a team to build reliable, scalable and high performance software that are easy to use by engineers worldwide
Develop software tools in C/C++ to support DFT/ATPG
Research and develop software solutions to allow greater efficiency in software architecture and algorithm optimizations
What We Need To See
MS/PhD in Computer Engineering, Computer Science, Electrical Engineering, or equivalent.
Experienced with modern C++, Unix/Linux and scripting
Experienced with static and dynamic code analysis tools
Solid understanding of algorithms, computer architecture and computer science theory
Passionate about SW development processes
Flexibility/adaptability for working in a dynamic environment with different frameworks and requirements
Excellent communication, interpersonal and customer collaboration skills
Ways To Stand Out From The Crowd
Experience in VLSI and/or DFT/ATPG.
Experience with multi-threading and distributed software
Experience in algorithmic and computational software
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence’s Intelligent System Design™ strategy, are essential for the world’s leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the world’s top 100 best-managed companies. Cadence solutions offer limitless opportunities—learn more at www.cadence.com.
