Job Description

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
• 15 years of experience in SoC architecture, specifically focusing on imaging (JPEG), video (H.264, H.265, AV1) and Image Signal Processor (ISP).
• Experience in Complementary Metal Oxide Semiconductor (CMOS) image sensor architecture.
• Experience in writing architecture specifications.

Preferred qualifications:

• Master’s degree or PhD in Electrical Engineering, Computer Engineering, or a related field.
• Experience working with various Software Driver teams.
• Familiarity with deploying neural networks on specialized hardware (e.g., Neural Processing Units (NPUs)/TPUs) for imaging tasks (e.g., AI-based denoising or super-resolution).
• Knowledge of MIPI interfaces (C-PHY/D-PHY) and memory subsystem interactions (DRAM/LPDDR).
• Knowledge of hardware/software interfaces.
  

Familiarity with deploying neural networks on specialized hardware (e.g., Neural Processing Units (NPUs)/TPUs) for imaging tasks (e.g., AI-based denoising or super-resolution).Familiarity with deploying neural networks on specialized hardware (e.g., Neural Processing Units (NPUs)/TPUs) for imaging tasks (e.g., AI-based denoising or super-resolution).Familiarity with deploying neural networks on specialized hardware (e.g., Neural Processing Units (NPUs)/TPUs) for imaging tasks (e.g., AI-based denoising or super-resolution).

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As a SoC Vision Architect in Google’s Silicon team, you will be at the heart of defining the hardware that powers the next generation of Google’s products. You will bridge the gap between AI research and physical silicon, architecting the Image Signal Processor (ISP), CODECS and the pixel data path. You will deliver unparalleled image quality while staying within the tight Power, Performance, and Area (PPA) constraints. You will participate in the concept, architecture, documentation, and implementation of a new product.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Define a flexible imaging pipeline hardware architecture, from the sensor interface (e.g., Mobile Industry Processor Interface (MIPI)) through the ISP, the encoder/decoder, scaling and memory output.
• Partner with Google research to transform advanced computational imaging algorithms into high-efficiency hardware logic.
• Conduct trade-off analyses between power, performance, and silicon area to meet thermal envelopes and current limitations.
• Influence external executive vendor roadmaps, ensuring deep co-optimization between their future products and Google’s custom silicon.
• Lead collaboration across Architecture, Register-Transfer Level (RTL), Physical Design and Validation teams.