Job Description

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 15 years of experience with power management or low-power design/methodology.
• Experience navigating the full product silicon/SoC delivery cycle, from initial architecture definition through to post-silicon productization.
• Experience with low-power architectures or advanced power optimization techniques.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture or power/performance analysis.
• Experience with any of the following: product characterization, DVFS governor, power analysis, thermal management, peak power management, in-rush current, PDN droop detection and mitigation, adaptive clock distribution, aging and process monitors, power aware floorplanning, battery technology, concurrency management and thermal management.
• Exceptional leadership and persuasion skills, with a demonstrated ability to influence cross-functional roadmaps and drive ROI-based technical decisions.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As the SoC Hardware Characterization Lead, you will be the principal technical owner bridging custom silicon and consumer hardware software teams, you will lead end-to-end post-silicon validation, debugging, and optimization across voltage, frequency, and power-management architectures. In this high-impact leadership role, you will architect scalable hardware-software frameworks to drive platform-level Power and Performance (P&P) optimization, maximize System-on-Chip (SoC) energy efficiency, and ensure system stability for product launch. Serving as the central technical authority across chip design, architecture, product test engineering, and system software, you will align cross-functional partners, streamline manufacturing test screens while safeguarding quality metrics, and lead an engineering team through complex debugging to deliver launch-critical milestones.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $240000 - $333000 (USD) + 25% bonus target + equity + benefits

Learn more about benefits at Google.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Responsibilities

• Own the bridging chip design, architecture, product engineering, and system software to architect scalable silicon-software frameworks, accelerate power-management deliverables, and drive continuous power, performance, and platform stability optimizations.
• Direct end-to-end post-silicon validation, characterization, and debugging across advanced voltage, frequency, and power architectures, ensuring physical silicon behavior aligns with architectural intent while driving cross-functional alignment on feature value and product trade-offs.
• Partner with engineering stakeholders to optimize manufacturing test processes and production screening capabilities, fine-tuning voltage margins while safeguarding product quality standards and defect targets (DPPM).
• Mentor and guide a high-performing engineering team focused on complex system characterization, including operating limits (Fmax and Vmin), energy efficiency, and root-cause hardware stability debugging.
• Drive the long-term technology roadmap for sensing subsystems (voltage, current, and temperature) and hardware trigger mechanisms to address rising current densities and industry trends.