Our clients are a leading technology company specialising in the design and development of cutting-edge, customised server hardware solutions optimised for artificial intelligence and machine learning applications.

 

Their mission is to empower businesses and researchers to accelerate their AI initiatives by providing them with high-performance,
scalable, and energy-efficient hardware infrastructure. As a rapidly growing company at the forefront of AI hardware innovation, they are constantly seeking talented and motivated individuals to join their team. They offer a  dynamic and challenging work environment, with opportunities to make a significant impact on the future of AI technology.
This is an architect role in which you will be defining the architecture of the next generation of Machine Learning ASICs being built on the modern process technologies and featuring industry leading performance and feature sets.

 

Responsibilities

 

 Develop architectural definition of upcoming products to include IP, Fabric and SOC
architectures
 Lead and manage the definition, design, verification, and documentation processes
throughout the SoC development lifecycle
 Contribute to the development of micro-architectural specifications and feature
definitions
 Perform RTL logic design and simulation for functional units, subsystems, and
complete SoC chip designs
 Evaluate and balance design trade-offs related to modularity, scalability, design-for-
test (DFT) requirements, power efficiency, area constraints, and performance
optimization
 Leverage strong written and verbal communication skills to effectively collaborate
with internal teams and external customers
Requirements
 10+ years of prior experience in defining and delivering high performance ASICs
into production, with focus on architecture definition and performance analysis
 Experience and knowledge of Computer Architecture concepts such as
microprocessor architecture, memory systems, on-chip interconnection networks,
hardware/software partitioning etc.
 Proficient in integrating components or IP blocks from both internal and external
sources
 Experienced in RTL/logic design for ASICs, IP blocks, or SoCs using SystemVerilog
RTL coding

 Knowledge of low-power design techniques and advanced process nodes is a plus