Job Description
Minimum qualifications:
- Bachelor degree in Computer Science, Electrical Engineering, or equivalent practical experience.
- 8 years of experience in developing test and debug infrastructure such software tools, lab equipment and test lab automation scripting.
- Experience in coding languages such as C, C++ or Python.
Preferred qualifications:
- Master's degree in Computer Science, Electrical Engineering, or equivalent practical experience.
- DDRPHY and DRAM Tuning and Characterization experience over Process, Temperature, Voltage (PVT).
- Familiarity with using Prototyping platforms like Emulators or Field Programmable Gate Array (FPGAs).
- Familiarity with power and performance measurement of SoCs.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities
- Collaborate with Architecture, Design and product teams to understand requirements for memory subsystem validation Double Data Rate Physical Layer (DDRPHY), Memory Controller, Dynamic random-access memory (DRAM).
- Understand the design and develop/execute validation tests to establish functionality of the new design on emulation platform for tapeout for DDRPHY and DRAM subsystem.
- Drive post-silicon bringup and validation activities for the DDRPHY/DRAM interface including its tuning and characterization.
- Develop various post-silicon validation, debug, margin tools related to DDRPHY and DRAM.
