Job Description

Meta's Reality Labs silicon team is building custom chips that power the next generation of augmented and virtual reality devices, including headsets and wearables. As a Silicon Power Architect, you will define and drive power architecture strategy across the full silicon stack — from microarchitecture and power delivery networks to firmware-level power management — ensuring that our custom AR/VR SoCs meet aggressive power, thermal, and performance targets required for immersive, always-on wearable experiences. In this role, you will shape long-term power roadmaps and influence chip architecture decisions that directly determine the viability and user experience of Reality Labs products.

Responsibilities

Define and own the power architecture strategy for custom AR/VR SoCs, spanning microarchitecture, power domains, clock gating, and voltage scaling schemes

• Develop power budgets and power delivery network specifications in collaboration with circuit design, package, and board engineering teams
• Drive power modeling and estimation methodologies across pre-silicon and post-silicon phases to validate architectural decisions
• Establish power management frameworks including dynamic voltage and frequency scaling, power gating policies, and thermal throttling strategies for wearable form factors
• Partner with firmware and software teams to define hardware-software power management interfaces and runtime power control mechanisms
• Lead cross-functional architecture reviews, communicating power trade-offs and design decisions to chip architects, RTL engineers, and product stakeholders
• Analyze power measurement data from silicon bring-up and characterization to identify optimization opportunities and feed learnings back into future architecture generations
• Define power architecture requirements for IP blocks and third-party vendor components integrated into Reality Labs SoCs
• Develop long-term power roadmaps aligned with the product roadmap for AR/VR headsets and wearable devices, anticipating technology scaling challenges
• Mentor other engineers on power architecture methodologies and contribute to the broader silicon engineering organization's technical standards

Qualifications

8+ years of experience in silicon power architecture, SoC power management, or related chip architecture disciplines

• Experience defining power architectures for mobile, wearable, or consumer SoCs, including power domain partitioning, DVFS, and power gating design
• Experience developing power models and budgets across microarchitecture, RTL, and post-silicon stages of the chip development lifecycle
• Experience collaborating with circuit design, physical design, and firmware teams to co-optimize power delivery and power management solutions
• Experience communicating architectural trade-offs and technical decisions through written proposals and cross-functional design reviews Experience with power architecture for AR, VR, or other wearable consumer electronics SoCs with stringent thermal and battery life constraints
• Familiarity with power delivery network design, on-chip voltage regulation, and package-level power integrity analysis
• Experience defining hardware-software co-design interfaces for runtime power management in embedded or real-time operating environments
• Background in post-silicon power characterization, measurement methodologies, and correlation of pre-silicon power models to silicon results