Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience in ASIC physical design flows with emphasis on physical verification convergence and tapeout signoff.
• Experience in physical verification tools, Python, Tcl, or Perl scripting.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience in place and route (PnR) tools like fusion compiler or innovus with physical convergence.
• Experience in padrings, bumps, redistribution layer (RDL), and IP integration (e.g., memories, input/outputs, and analog IPs).
• Knowledge of semiconductor device physics and translator characteristics.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Physical Design Verification Engineer, you will collaborate with physical design, circuits, technology, and package leads and drive the overall sign-off physical convergence for high-performance designs. You will also define the overall physical convergence methodology, plan out the timelines, and work closely with the block owners to achieve physical convergence through systematic fixes and minimal manual effort.

In this role, you will perform technical evaluations of electronic design automation (EDA) tools, process nodes, and IPs and provide recommendations. You will participate in the development of exceptional technology in high-performance computing.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Own and perform physical verification steps including design rule check (DRC), layout versus schematic (LVS), electrical rule check (ERC), design for manufacturing (DFM) at the block, subsystem, and full chip level.
• Own and define process flow and methodology for full chip assembly and tapeout signoff.
• Work with floorplan and physical design engineers to drive physical verification convergence.
• Perform technical physical evaluations of vendors, process nodes, and intellectual property (IP).
• Contribute to design methodologies and automation scripts for physical verification steps.