Job Description

As a Silicon Photonics PIC Architect you will engage in the development of advanced silicon photonics integrated circuits-based products. You will take responsibility for the design of complex photonic devices and interconnects, as well as systems-on-chip, from design through fabrication, testing and analysis. As a member of our silicon photonics design team, you’ll be working alongside other experienced and multidisciplinary teams and agile silicon photonics designers with strong records of delivering innovative photonic device designs and large-scale silicon photonics circuits.

You will contribute to the design and development of complex photonic integrated circuits and systems for next-generation coherent transceiver technologies. As the PIC Development Engineer you will work with the PIC team and other cross-functional teams to provide the performance, power, and area estimates of the next-generation optical front-end solutions. You will assist in the development of new design approaches and work to innovate on both device-level design and system-level optimization working with cross-functional teams and collaborating to deliver co-designed and co-optimized photonics chips. You will also be responsible to deliver the manufacturing requirements of your designs, as it pertains to the foundry or OSAT limitations. You will be accountable for delivering the PICs and make design decisions as required by product specifications and schedule.

The PIC Development Engineer will be responsible for the integration of the photonic IC in optical engines and will interface with mixed signal, substrate, packaging, and simulation teams to ensure system requirements are met for co-designed and co-optimized photonics chips. This also involves:

• Owning Tx and Rx PIC designs and communicating expected performance and PIC requirements to cross-functional teams. Evaluate optical link budgets, RF performance and power consumption and verify performance compared to requirements.
• Defining test requirements and collaborate with test team to prepare test plans that provide coverage and address requirements.
• Defining PIC reliability requirements and collaborate with reliability team to generate reliability plans.
• Owning and generating PIC performance documents to track performance across R&D and production design variants.
• Managing the overall system PIC fabrication and assembly track, closely interacting with the involved teams. Interact with fabrication partners and product engineering team.
• Help Evaluate new design approaches and innovate on both device-level design and system-level optimization.
• Contributing expertise to experimental evaluation of the integrated photonic devices/systems solutions (i.e., assessing feasibility/risk of integrating hybrid devices).
• Leading task force of designers to support the design of active photonic device components for next-generation development for hybrid-integration, III-V, and L-band programs.
  

You have:

• Ph.D. in electrical engineering / physics / applied physics / similar quantitative fields and 5+ years experience working in relevant fields.
• Experience working on and modelling complex photonics circuits and systems.
• Experience with designing or characterizing silicon photonic or other integrated optical/optoelectronic devices or circuits; experience developing components for optical I/O, including edge or fiber couplers, grating couplers, etc.
• Solid knowledge of object-oriented programming, as well as skills in Python or C/C++
• Good understanding of general concepts in physics, especially in optics and electromagnetics. Understanding of general concepts in fiber optics and integrated optics.

It would be nice if you also had:

• Experience with high-frequency (RF) design and modeling.
• Experience with epitaxial growth and design, and hybrid integration. Experience with controls theory and implementation. Experience in TCAD modeling.
• Proficiency with optics design tools, such as Lumerical. Experience in photonic integrated circuit design, scattering and transfer matrix approaches, and layout generation.