Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience in circuit design, physical design (RTL-to-GDS), or technology development, including nodes (e.g., 7nm or below).
• Experience with SPICE and transistor level design in nodes.
• Experience with concurrent optimization across custom circuit/IP and physical design, including Place and Route (PNR) and Static Timing Analysis (STA).
• Experience in CMOS device physics, finfet/GAA/nanosheet architectures, or layout parasitics, and in scripting or automation in one or more programming languages (e.g., Tcl, Python, or Perl).

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience with scripting languages such as Perl, Python, or Tcl.
  
• Experience working with foundry technology files (PDKs), standard cell libraries, metal stacks, and other features. Understanding of collaterals for front-end and back-end design teams.
• Track record of delivering optimized custom circuits/memories/IPs and PNR blocks for product tapeout.
• Understanding of characterization and verification of standard cells/SRAMs/register files, including knowledge of power, noise, variation, and IR analysis.
• Strong documentation and presentation skills to communicate efficiently with teammates and vendors/partners.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You will be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You will contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML driven systems.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Evaluate, analyze, implement, and integrate SRAMs, other memories (such as multiport register files), and custom circuits. Drive proper IP integration and margins with the physical design team.
• Work with the foundry, IP partners, and the technology, physical design, and architecture teams in advanced CMOS nodes to optimize our products for PPA, schedule, and reliability.
• Drive and support test chip design, execution, and validation of critical circuit IPs.
• Design and build custom circuits at the transistor and gate levels to support physical design and power-performance-area optimization.
• Drive development of a leading edge technology platform for custom, high performance ASIC’s and SoC’s, from design through manufacturing, packaging, and test.