Minimum qualifications:

• Bachelor's degree in Electrical Engineering, or a related field, or equivalent practical experience.
• 2 years of experience with Design For Test (DFT) methodologies, DFT verification, and industry-standard DFT tools.
• Experience with scan insertion, ATPG, gate level simulations and silicon debug, low power designs, BIST, JTAG, IJTAG tools and flow.
• Experience in SoC designs and integration flows.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, or a related field.
• 1 year of experience with development projects in Very-Large-Scale Integration (VLSI).
• Experience scripting in Python or Perl or other related language.
  
• Experience or understanding of RTL design, SoC architecture, verification.

About the job

In this role, you will help create the custom hardware, software, and networking technologies that power all of Google's services. You will focus on DFT implementation, generating test patterns, and validating them for post-silicon testing. You will own the entire process, from low-level circuit design to high-volume manufacturing. You will ensure the reliability of the custom silicon inside our data centers, ultimately impacting millions of users worldwide.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving team behind Google's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Implement DFT Register-Transfer Level (RTL) logic and validate the same. Generate and validate Automatic Test Pattern Generation (ATPG) test patterns for various SoC blocks under executive guidance.
• Implement and verify basic DFT logic like scan, MBIST, and boundary scan architectures.
• Perform gate-level simulations to verify the timing and functionality of specific test modes.
• Assist the team in post-silicon testing and debugging failure logs from Automated Test Equipment (ATE) data.
• Maintain and run automation scripts in Python or Tcl for standard DFT workflows.