Job Description

Company:

Qualcomm Technologies International Ltd

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

Qualcomm is seeking talented Physical Design Engineers to join the Nuvia CPU team in Cambridge, UK The team is developing next-generation, high-performance, power-efficient custom CPU cores for advanced compute and server-class platforms that will help transform the industry.

This is an opportunity to work with some of the most talented and passionate engineers in the world to create CPU designs that push the limits of performance, energy efficiency, and scalability You will collaborate with global teams across CPU architecture, RTL design, circuit design, CAD, SoC integration, timing, power, and post-silicon validation.

This position is open from Senior Engineer through Staff Engineer level, with responsibilities, ownership, and technical leadership scaled according to experience.

Key Responsibilities will include

As a Server CPU Physical Design Engineer, you will:

• Own or contribute to CPU block implementation from RTL/netlist to GDS, including synthesis, floorplanning, power planning, placement, clock tree synthesis, routing, optimization, ECOs, and signoff.
• Drive timing closure and physical implementation convergence across multiple modes, corners, and operating conditions.
• Work on high-performance, low-power CPU designs with demanding performance, power, and area targets
• Debug and resolve complex implementation issues related to timing, congestion, clocking, routing, IR drop, power integrity, EM, ECO closure, DRC/LVS, and physical verification.
• Collaborate closely with RTL, architecture, circuits, CAD, SoC, and post-silicon teams to improve design quality, implementation efficiency, and product performance.
• Evaluate and contribute to the design process from concept through productization, including architecture definition, feasibility analysis, pre-silicon design and verification, and post-silicon validation.
• Develop and enhance physical design flows, automation, and methodologies to improve productivity and quality of results.
• Use data-driven analysis to identify implementation bottlenecks, improve design convergence, and push PPA beyond standard targets.
• For Staff-level candidates, provide technical leadership, mentor engineers, define implementation strategies, and drive closure of critical CPU blocks or methodology initiatives.

Required Skills and Experience

We are looking for candidates with experience in one or more areas of CPU, ASIC, or high-performance digital physical design

The ideal candidate will have:

• Strong experience in physical design implementation, including synthesis, floorplanning, placement, CTS, routing, timing closure, ECOs, and signoff.
• Strong understanding of static timing analysis and timing closure methodologies, including trade-offs between timing, power, area, congestion, and routability.
• Knowledge of high-performance and low-power implementation techniques.
• Hands-on experience with industry-standard EDA tools for synthesis, place and route, STA, power analysis, physical verification, and signoff, such as Genus, Innovus, Fusion Compiler, PrimeTime, Tempus, Voltus, RedHawk, Conformal, or equivalent tools.
• Ability to debug complex physical design issues across timing, congestion, clocking, routing, power, and verification domains.
• Scripting and automation experience using one or more of TCL, Python, or Perl
• Strong communication skills and the ability to work effectively in a global, cross-functional engineering environment.

Minimum Qualifications

Candidates should typically have one of the following:

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with relevant experience in ASIC, CPU, or physical design implementation.

OR

• Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with relevant hardware engineering experience.

OR

• PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with relevant CPU, ASIC, or physical implementation experience.

The exact experience level will depend on grade, with the role open from Senior Engineer through Staff Engineer

Preferred Qualifications

Experience in any of the following areas would be advantageous:

• Physical design experience on CPU cores, high-performance compute blocks, or timing-critical ASIC designs.
• Experience working in advanced semiconductor process nodes, especially 7nm and below
• Strong understanding of CPU PPA optimization and design convergence.
• Experience with low-power design techniques, clock optimization, useful skew, standard-cell library usage, and physical-aware optimization.
• Knowledge of power integrity, IR drop, EM analysis, and power signoff.
• Experience with timing ECOs and late-stage design closure across large scenario sets.
• Understanding of CPU microarchitecture, logic design, or circuit-level implementation considerations.
• Experience developing physical design methodology, automation, or productivity-enhancing flows.
• For Staff-level candidates, proven ability to lead complex technical work, influence cross-functional teams, and mentor other engineers.

What We Value

We are especially interested in engineers who:

• Have strong physical design fundamentals and enjoy solving difficult implementation problems.
• Are passionate about pushing performance, power, and area to best-in-class levels.
• Can work independently while collaborating effectively across global teams.
• Bring a structured, analytical approach to debug, optimization, and design closure.
• Are motivated by the opportunity to build high-performance, power-efficient server CPU products.
• Demonstrate ownership, technical curiosity, and a continuous-improvement mindset.

Benefits and Perks

At Qualcomm, you will be part of a collaborative engineering culture focused on innovation, technical excellence, and meaningful product impact.

We offer:

• Competitive compensation package, including base salary, performance-related bonus, and equity opportunities.
• Employee Stock Purchase Plan and equity programs, supporting employee share ownership and long-term participation in Qualcomm’s success.
• Pension and retirement support, including a matching pension scheme.
• Health and wellbeing benefits, including medical, life, income protection, and wellbeing resources.
• Maternity, paternity, family, and extended leave support to help employees balance professional and personal commitments.
• Education assistance and tuition support to enable continued learning and professional development.
• Relocation and immigration support where applicable, particularly for the right candidates moving to join the team.
• Employee assistance and resilience programs supporting mental wellbeing, balance, and personal resilience.
• Opportunities to connect through employee networks, community programs, volunteering, and social groups that support inclusion, collaboration, and community engagement.
• Subsidised wellbeing and lifestyle benefits, which may include gym or fitness support, bicycle purchase schemes, and employee clubs.
• A flexible, collaborative, and technically challenging work environment, with the opportunity to work alongside highly skilled engineers on advanced CPU technology.

Why Join the Nuvia Data Center CPU Team in Cambridge?

Cambridge is Qualcomm’s largest office in the UK, with approximately 400 team members across engineering, business strategy, and support functions. From an engineering perspective, the Cambridge site includes teams focused on RF and PMU analog design, digital design and verification, digital physical design, embedded software, packaging, and post-silicon validation. Target products include high-performance CPUs and GPUs, ultra-low-power IoT devices, and wearables such as smart glasses, smart watches, and earbuds.

The Nuvia Data Center CPU team offers the opportunity to work on advanced custom CPU technology for next-generation compute platforms. You will be part of a world-class engineering team tackling demanding server-class CPU implementation challenges in advanced technology nodes.

This is a role for engineers who want to make a direct technical impact, contribute to high-performance CPU designs, and help shape the future of energy-efficient server computing.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field.

*References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

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