Job Description

• The Role and Impact
  As an Analog Circuit Design Engineer, you will play a pivotal role in defining, designing, and optimizing high speed SerDes circuits to power Intel's next-generation technologies. Your contributions will directly drive innovation and elevate Intel's leadership in advanced high-speed communication systems and memory interface PHY designs.
• Collaborating with cross-functional teams, you will ensure breakthroughs in power, performance, and area efficiency while supporting the development of robust and reliable analog solutions. This is your opportunity to make a tangible impact on Intel's cutting-edge process nodes and cutting-edge products that shape the future of technology.
  
  Key Responsibilities
  - Design, develop, and optimize analog circuits for high-performance and high-speed Ethernet SerDes applications.
  - Perform circuit design, floor planning, and simulation using advanced tools to develop accurate analog behavior models.
  - Evaluate circuit functionality and develop methodologies to optimize power, performance, area, timing, and yield goals.
  - Collaborate with architecture, layout, and validation teams to ensure circuits meet functionality and electrical robustness requirements.
  - Support silicon validation, lab measurements, and debug pre- and post-silicon issues for analog and mixed-signal circuits.
  - Actively contribute to technical discussions, design reviews, and the development of design methodologies and best practices.
  - Mentor and guide junior engineers to foster technical growth and enhance team productivity.

Qualifications:

Minimum Qualifications
- Bachelor’s degree in electrical engineering, Electronics Engineering, or a related field.
- 9+ years of experience with a bachelor’s degree
- Proficiency in designing high-speed circuits such as transmitters, receivers, clocking circuits, PLLs
- Experience in technical execution and leadership in high speed SerDes
- Strong fundamentals in CMOS design, RC circuits, and high-speed circuit design principles.
- Expertise with industry analog and mixed-signal design tools such as HSPICE, and MATLAB.
- Hands-on experience with advanced FinFET CMOS process technologies.
- Familiarity with high-speed communication standards such as Ethernet.
- Proven ability to debug and validate circuits during silicon and system-level testing.

Preferred Qualifications
- Masters with 7+ years of experience or Ph.D with 5+ years in Electrical Engineering, Electronics Engineering, or a related discipline.
- Experience with 224G+ SerDes architecture and development
- In-depth knowledge of equalization techniques, channel modeling, and transmitter/receiver optimization.
- Exposure to next-generation standards and architectures
- Demonstrated ability to work effectively in cross-functional teams and lead design decisions.
- Strong analytical, debugging, and problem-solving skills, with an eagerness to innovate and share knowledge.

Join Intel and contribute to creating technologies that transform industries and improve lives worldwide. Apply today to shape the future with us.

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Additional Locations:

Business group:

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.