Job Description

NextSilicon is reimagining high-performance computing. Our accelerated compute solutions leverage intelligent adaptive algorithms to vastly accelerate supercomputers, driving them forward into a new generation. Our new software-defined hardware architecture enables HPC to fulfill its promise of breakthroughs in all fields of advanced research.

At NextSilicon, everything we do is guided by three core values:

• Professionalism We strive for exceptional results through professionalism and unwavering dedication to quality and performance.
• Unity Collaboration is key to success. That's why we foster a work environment where every employee can feel valued and heard.
• Impact We're passionate about developing technologies that make a meaningful impact on industries, communities, and individuals worldwide.

We are looking for a highly motivated and detail-oriented Junior Design Verification Engineer to join our dynamic hardware engineering team. The verification team is responsible for ensuring the absolute functional correctness and quality of our next-generation ASIC/SoC designs before tapeout. In this foundational and collaborative role, you will work closely with senior verification experts and RTL designers, learn industry-leading verification methodologies, and contribute directly to the successful delivery of complex silicon.

Requirements

• B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
• 0-3 years of experience in ASIC/SoC design verification (relevant academic projects or internships are highly valued).
• Solid understanding of digital logic design architecture and fundamentals. Proficiency in Hardware Description Languages (SystemVerilog, Verilog) and/or Object-Oriented Programming (C++, Python).
• Basic knowledge of UVM (Universal Verification Methodology). Familiarity with basic verification concepts, including testbenches and logic simulation.
• Fluent in written and spoken English.
• Strong analytical and problem-solving skills, eager to learn and adapt, excellent team player with strong communication skills, and a high degree of self-motivation.

Responsibilities

• Develop, maintain, and execute block-level testbenches under the guidance of senior verification engineers.
• Write and execute directed and random test cases to thoroughly verify digital logic functionality.
• Debug simulation failures, identify root causes, and collaborate with design engineers to resolve RTL bugs.
• Implement, collect, and analyze coverage metrics (code coverage and functional coverage) to ensure verification completeness.
• Develop and maintain scripting tools (Python, Perl, Bash, or TCL) to automate verification flows and regression testing.
• Participate in verification plan reviews, document test environments, and actively contribute to the team's overall verification strategy.