Job Description

NextSilicon is reimagining high-performance computing. Our accelerated compute solutions leverage intelligent adaptive algorithms to vastly accelerate supercomputers, driving them forward into a new generation. Our new software-defined hardware architecture enables HPC to fulfill its promise of breakthroughs in all fields of advanced research.

At NextSilicon, everything we do is guided by three core values:

• Professionalism We strive for exceptional results through professionalism and unwavering dedication to quality and performance.
• Unity Collaboration is key to success. That's why we foster a work environment where every employee can feel valued and heard.
• Impact We're passionate about developing technologies that make a meaningful impact on industries, communities, and individuals worldwide.

We are looking for a curious and driven RTL Design Intern to join our Hardware Design team. This is a hands-on internship where you will work directly alongside experienced hardware architects and design engineers, gaining real exposure to the full RTL development flow in a world-class compute accelerator program. Whether you are a B.Sc. or M.Sc. student, you will be given meaningful work, close mentorship, and the opportunity to make a tangible contribution to silicon that ships.

Requirements

• Currently pursuing a B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or a related field
• Coursework or project experience in digital design: logic design, sequential circuits, or computer architecture
• Exposure to HDL coding in SystemVerilog or VHDL — from coursework, lab projects, or personal projects
• Familiarity with simulation tools and waveform debugging (e.g. ModelSim, Questa, or equivalent)
• Basic scripting skills in Python or Tcl for task automation: an advantage
• Understanding of AXI4 / AMBA bus protocols: an advantage
• Strong analytical mindset, eagerness to learn, and ability to take ownership of assigned tasks
• Good communication skills; comfortable working in a collaborative engineering environment

Responsibilities

• Implement RTL modules in SystemVerilog under the guidance of senior design engineers
• Run and analyze simulations to verify RTL block functionality; debug issues in waveform viewers
• Develop and maintain helper scripts (Python / Tcl) to automate repetitive design and verification tasks
• Participate in design and code review sessions, learning best practices in production RTL development
• Participate in the adoption of the AI methodologies in the digital design practice and design flow
• Document design decisions and findings clearly to support knowledge sharing within the team
• Collaborate with cross-functional teams including verification, physical design, and architecture