Job Description

Chain Reaction designs and builds hardware that fuels disruptive blockchain technologies by accelerating compute performance. Our world class teams are transforming the future of data, creating the infrastructure that will power the next generation of secure, scalable, green computing. The main bottleneck in scaling cutting edge solutions in privacy tech, data-analysis and real-time computing is acceleration – existing hardware cannot keep up with data processing needs. Chain Reaction’s products reshape how data is processed and used on a global scale, and we’re looking for the brightest people to join us.

We are looking for talented and ambitious individuals to join our Yoqneam IC team.

Roles and responsibilities

• The candidate will join our BE team, focusing on Full-Chip floor-planning, timing closure and integration, collaborating closely with frontend design, architecture, physical design, and analog teams. Additionally, the candidate will provide support to design teams across various methodologies and contribute to project execution efforts.
• What will the candidate be doing
• Lead Full Chip Layout activities & methodologies for a brand new SoC, from definition to Tape Out.
• Floor Planning Top to Bottom & Bottom up – FC, Sub System & Block level.
• Involved in chip architecture, in close collaboration with the packaging, design & architecture teams. Exploring different floorplan structures to achieve both best area & ease of convergence.
• Drive sign-off timing convergence for high performance designs at Full-chip and building block level.
• Involved in definition of overall STA methodology, STA infrastructure and sign-off convergence flows, working closely with block owners throughout the project for sign-off timing convergence.
• Work closely with EDA (Electronic Design Automation) vendors on latest tool feature development and qualification.

Requirements

• BSc or MSc in Electrical Engineering or Computer Engineering.
• 8+ years experience in full chip design.
• Experience in leading the full-chip level design and successfully taping out multiple intricate SoCs.
• Experience in floor planning, integration, signoff methodologies, and signoff tools for hierarchical designs.
• Experience with SoC design practices such as multiple voltage and clock domains, integration of mixed-signal IPs and I/O integration.
• Expert knowledge of the entire backend design flow from RTL to TO.
• Experience with STA (Static Timing Analysis) tools like primetime or tempus.
• Experience with IR drop tools like Ansys Redhawk or Volta's.
• Physical Verification Expert (DRC/LVS).
• Strong independent and motivated to learn quickly, hard-working, and is results oriented.
• Good social skills and ability to work collaboratively with other teams.

Preferred

• Experience with high-speed serial interfaces such as PCIe, DDR, Ethernet.
• Familiarity with advanced DFT flows & tools.
• Strong proficiency in scripting language, such as, Perl, Tcl, Python, Make, and automation methods/algorithms.