Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field, or equivalent practical experience.
• 8 years of experience in design verification with a focus on mixed-signal, PHY layers, DSP, communication systems, or arithmetic logic blocks.
• Experience with scripting in Python, Perl, or Makefile for automation.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related technical field.
• Experience with mixed-signal verification tools (e.g., verilog-AMS, Real Number Modeling (RNM), or SystemVerilog-AMS).
• Experience leading verification through a full silicon life cycle (plan to tape-out).
• Experience with performance verification (throughput, latency, and power modeling).
• Experience in formal verification (JasperGold or similar) for complex state machines.
• Understanding of adaptive algorithms (FFE/DFE) and how to verify loop stability in a digital environment.

About the job

In this role, you own the verification strategy for high-speed Physical Layer (PHY). You aren't just looking for RTL bugs, you are looking for system-level failures. You will lead the effort to verify how the digital DSP interacts with the analog front-end.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities

• Lead the verification strategy for high-speed PHYs (112G/224G), defining the test plan for top-level integration and mixed-signal boundaries.
• Architect and implement mixed-signal verification flows using Real Number Modeling (RNM) or SystemVerilog-AMS to verify the interaction between Analog Front Ends (AFE) and digital DSP.
• Design specialized testbenches to verify the stability, convergence time, and tracking capabilities of adaptive algorithms (e.g., LMS, Zero-Forcing) across Process, Voltage, Temperature (PVT) corners.
• Develop tests that simulate real-world data center conditions, including link bring-up, auto-negotiation, and error-recovery protocols.
• Act as the primary verification interface for the Signal integrity and Power Integrity (SI/PI) and Analog teams, ensuring that physical channel impairments (loss, crosstalk, reflections) are accurately reflected in the Design Verification (DV) environment.