Job Description

Job Summary

JD for Functional Safety assessment lead.

• Min 12+ years of FPGA or SoC architecture design and implementation/integration experience
• Experience working in ARM/RISC-V processor subsystem and AXI/APB protocol/NOC
• Expertise on Functional Safety ISO 26262 standard for hardware and silicon
• Expertise in performing safety analysis (IP level or full chip level)
• Expertise in defining the safety requirement, TSC and safety mechanism.
• Expertise in performing the design FMEA and FMEDA (IP level or full chip level)
• Expertise in safety analysis at design level and using EDA tool Synopsys or Siemens Mentor
• Strong understanding on fault injection simulation concept and signoff
• Expertise in establishing traceability using tool (ex: JAMA or Doors etc.)
• Strong expertise understanding on Functional Safety ISO 26262 process and work product
• Expertise in FUSA work product signoff and developed the safety manual.
• Demonstrated expertise in independently performing the detailed design analysis and I3 conformance review (ASIL-D)
• Demonstrated expertise in independently handling the FUSA audit and assessment for IP level or full chip level
• Demonstrated expertise in defending process gap and work product review with customer stakeholder
• Able to support customer on process improvement
• Excellent oral and written communication skill

Able to drive the team and stakeholder management

Key Responsibilities

Fusa

Skill Requirements

Other Requirements