Job Description

• Develop and integrate iterative timing closure flows for advanced APR (Automated Place and Route) in EDA tools to achieve PPA convergence on new process nodes/PDKs.
• Drive team to utilize and improve AI agents to improve PPA experiments and RTL2GDS workflow.
• Drive DTCO (Design-Technology Co-Optimization) experiments across multiple PPA objectives.
• Work with Intel Foundry team to ensure platform entitlement is reflected in Intel Products TFM.
• Lead team to debug PPA non-determinism and regressions, drive improvements with EDA vendors and foundry team.
• Align stakeholders to determine PPA measurement methodology during TFM release.
• Drive deterministic measurement of PPA for every TFM release.

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

• B.S. or M.S. in Computer Science, Computer Engineering, Computer Engineering, Electrical Engineering, Data Science, or related disciplines.
• 10+ years of relevant industry experience in software development, data engineering, analytics, or AI related roles.
• Experience working on PPA convergence and structural design (RTL2GDS) for several product tape-ins.
• Deep expertise in working with EDA design construction tools, including knowledge for application options, commands and tool configurations.

The ideal candidate demonstrates strong analytical thinking, problem solving, and debugging skills, communicates clearly and effectively in written and spoken English, and thrives in a fast paced, collaborative environment. The individual is self-motivated, capable of working independently, able to manage multiple priorities effectively, and is willing to rotate across projects to expand technical depth, AI expertise, and overall engineering impact.

Job Type:

Experienced Hire

Shift:

Shift 1 (Malaysia)

Primary Location:

Malaysia, Penang

Additional Locations:

Business group:

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.