Job Description

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 15 years of experience with verification methodologies and languages, such as UVM and SystemVerilog.
• Experience leading a functional verification team for ARM or X86 compliant processor-based products.
• Experience with functional verification and performance validation of modern mobile processors, micro-architecture, and related technologies.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• 15 years of experience in industry design verification.
• Experience in ISAs, X86, and RISC-V.
• Knowledge of general purpose operating systems such as Linux and Android.
• Knowledge of ARM Instruction Set Architecture (ISAs).

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $240000 - $333000 (USD) + 25% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities

• Lead the definition of verification architectures and methodologies for complex ASIC and SoC designs.
• Drive the overall verification strategy, including test planning, testbench development, and coverage closure metrics.
• Architect advanced verification environments using SystemVerilog and UVM to ensure maximum test coverage.
• Define formal verification strategies to mathematically prove design correctness for critical hardware blocks.
• Establish emulation and post-silicon validation plans to accelerate system-level integration and debugging.