职位描述

Responsibilities
ISP Module / Sub-System Ownership
Own the micro-architecture and RTL of key ISP blocks or sub-systems end-to-end, from spec definition through tape-out and mass production.
Architecture & PPA Leadership
Drive pipeline-level dataflow, buffering strategy and interface design; lead PPA trade-offs across image quality, area, bandwidth and power; deliver architecture and μArch specifications.
Cross-Team Collaboration
Partner deeply with algorithm, tuning, SW / driver, DV and backend teams; align on reference-model strategy, register interfaces and convergence plans.
Silicon Bring-up & Productization
Lead silicon-stage image-quality debug, root-cause analysis and RTL ECOs; ensure smooth ramp to mass production.
Technical Leadership
Mentor mid-level and junior engineers; drive design methodology, code quality, low-power (UPF), CDC / RDC and documentation standards across the team.

职位要求

Requirements
Basic
BS or above in Microelectronics / EE / Communications / CS or related field.
5+ years of digital IC front-end experience, with at least one taped-out chip containing ISP as a key contributor or module owner.
Strong proficiency in Verilog / SystemVerilog and SVA.
Proficient with mainstream EDA tools (VCS / Verdi / SpyGlass / DC); familiar with JasperGold / VC Formal.
Solid experience with AMBA protocols and high-bandwidth DMA design.
ISP Domain
Deep understanding of the full camera imaging pipeline; able to articulate the physical meaning, image-quality impact and hardware implementation of each stage.
In-depth knowledge of mainstream CFA patterns and their hardware implications.
Strong engineering intuition for ISP bandwidth, line-buffer area and power budgets.
Proven ability to drive technical discussions with algorithm engineers on precision, approximation and hardware-friendliness.
Nice to Have
Hands-on experience with AI-ISP HW/SW co-design.
Experience with multi-camera fusion, bokeh, super-resolution or similar advanced imaging features.
Automotive ISP experience (HDR / LFM / ISO 26262).
Familiarity with MIPI CSI-2 and a broad range of sensor RAW characteristics.
Track record of leading a module from spec to sign-off.
Experience with commercial ISP IP (Arm Mali-C, VeriSilicon, etc.) or in-house ISP development.