Job Description

Lattice Overview

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Responsibilities & Skills

We are seeking a highly organized and results-driven Senior Software Engineer in the QA department. The engineer will be responsible for quality aspects and assessment of components under Lattice Radiant tool (Ex: Synthesis, Implementation, Timing Analysis, etc.)

Key Responsibilities:

• Verifying the accuracy and reliability of the static timing analysis (STA) software in Radiant

• Create and maintain test suites to ensure that STA correctly calculates path delays, handles complex constraints and accurately reports setup / hold violations for a variety of designs and running them in regression frameworks

• Monitor the regressions – analyze the failures and report them to fix

• Prepare and execute on test plans for upcoming features / changes in STA including multi corner analysis, signal integrity, clock domain crossing, etc.

• Ensure that the delay calculations by STA match with the HW expectations

Skill set (Mandatory):

• Very strong understanding of FPGA architectures

• Good understanding of Lattice Diamond / Radiant or similar FPGA tool flow

• Good experience with RTL using Verilog to create test designs for STA

• Strong understanding of constraints handling, preferably with SDC

• Exposure to timing analyser concepts and tools

• Strong debugging skills

Skill set (Good to have):

• Any experience to scripting languages like Python, Perl, TCL

• Experience with high speed I/O (PCIe, DDR) and their timing requirements

Qualifications:

• BS/MS in Electrical, Electronics or Computer Science or Computer Engineering.

• 5+ years of experience in EDA / RTL development / verification

• Excellent verbal & written communication skills with ability to interact with cross functional teams spread across different geographies.

• Experience in FPGAs is preferred.