Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
• 8 years of experience in Automatic Test Pattern Generation (ATPG) methods.
• Experience with multiple projects in DFT design and verification, DFT specification, definition, architecture, and insertion.
• Experience with DFT techniques and tools, ASIC DFT synthesis, simulation, and verification flow.
• Experience in leading DFT activities throughout an ASIC development flow.

Preferred qualifications:

• Master's degree in Electrical Engineering or a related field.
• Experience in JTAG and iJTAG protocols and architectures.
• Experience in post-silicon test or product engineering.
• Experience in SoC cycles, silicon bring-up, and silicon debug activities.
• Knowledge of fault modeling techniques.

About the job

In this role, you will play a crucial role in Design for Testing (DFT) Architecture and DFT design, and support devices of extreme complexity to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality matrix throughout the project life-cycle, and providing sign-off DFT to tapeout.

Responsibilities

• Lead and execute activities in the design, implementation, and verification of DFT solutions for large-scale ASICs.
• Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
• Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
• Manage the DFT team's workload and deliverables, provide technical leadership and guidance to the team.
• Lead DFT execution of a silicon project (e.g., planning, execution, tracking, quality, and signoff).