About the Role
The CEG NAG (Networking Architecture Group) is Intel's premier team focused on defining the future of high-performance networking silicon. Our team architects next-generation networking solutions that enable hyperscale data centers, cloud infrastructure, and AI workloads to achieve unprecedented performance and efficiency. We specialize in IPU/DPU platforms, advanced packet processing architectures, and programmable networking technologies that form the backbone of modern distributed computing systems.
We are seeking a Senior SoC Compute/Memory Subsystem Architect to define and drive the architecture of compute complexes and high-performance memory subsystems for next-generation IPU/DPU platforms.
This role is responsible for end-to-end architecture of CPU clusters, cache hierarchies, coherency models, and memory subsystems. You will optimize system-level performance, scalability, power efficiency, and programmability while ensuring seamless interaction with networking, storage, and accelerator subsystems in hyperscale environments.
What You’ll Do
Key responsibilities will include but not limited to:
Compute Subsystem Architecture
1. Define architecture for IPU compute complexes (e.g., ARM/x86 clusters), including core selection, scaling strategy, and configuration tradeoffs
2. Architect compute subsystem roles (control plane, data plane assist, offload execution, management services)
3. Drive compute architecture decisions balancing performance, power, and area
Cache Hierarchy and Coherency Architecture
1. Define and evolve multi-level cache hierarchy (private/shared caches, system-level cache)
2. Architect coherency models across compute cores, accelerators, and IO subsystems (coherent vs non-coherent interactions)
3. Evaluate tradeoffs between latency, bandwidth, scalability, and coherence domain complexity
Memory Subsystem Architecture
1. Architect system memory subsystems including:
2. Work with Performance architect in define memory access models for compute, network, and accelerator subsystems
3. Ensure optimal balance between latency-sensitive control workloads and bandwidth-intensive datapath workloads
IO Memory and Virtualization Architecture (SMMU/IOMMU)
1. Define architecture for SMMU/IOMMU supporting virtualization-heavy IPU workloads
2. Architect features such as:
3. Ensure efficient interaction between host, IPU/DPU compute, and offload engines
System-Level Integration (Compute Network Storage)
1. Architect integration between:
2. Optimize data movement across subsystems to minimize copies, latency, and bandwidth overhead.
3. Drive system architecture decisions for balanced SoC performance.
Power, Efficiency, and Scaling Strategy
1. Define compute and memory strategies for power efficiency and DVFS scalability.
2. Architect mechanisms for:
3. Optimize performance-per-watt at system level.
Multi-Generation Architecture Roadmap
1. Lead long-term roadmap for compute and memory evolution across IPU/DPU product generations
2. Define scaling strategies for:
3. Ensure backward compatibility and smooth migration across product lines
Cross-Functional Leadership
1. Collaborate with teams across:
2. Drive architecture alignment and resolve cross-domain tradeoff
Behavioral traits that we are looking for: (soft skills that you would like to see in a candidate)
Intel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life.
See Intel Benefits for more details.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Note:
For information on Intel’s immigration sponsorship guidelines, please see
Intel U.S. Immigration Sponsorship Information
Minimum Qualifications and Experience
Batchelor's degree in Electrical Engineering, Computer Engineering, or in a STEM related Field of Study.
You must have 7 + years of experience in the following:
Preferred Qualifications and Experience
Join us in building a brighter future through technology innovation!
Experienced Hire
Shift 1 (United States of America)
US, California, Santa Clara
US, Arizona, Phoenix, US, California, Folsom, US, California, San Jose, US, Colorado, Fort Collins, US, Texas, Austin
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel
Annual Salary Range for jobs which could be performed in the US: $164,470.00-269,100.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.The application window for this job posting is expected to end by 07/31/2026
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