Focus on high-speed interface PHY IP physical implementation, develop necessary scripts or tools to enhance current PD design flow. Work in product projects, including but not limited to: complete the project tasks; solve design issue and provide flow to check and avoid similar issue; analyze and summarize PPA optimization methodologies and results, implement optimal design parameters and flows for different projects.
-BS with minimum 9+ years of experience. MS with minimum 7+ years of experience.
-Strong physical design experience in the digital implementation domain including Floorplan, CTS, STA, Physical verification, Power analysis.
-Solid background in circuits, electronics, physics, be willing to learn new technology for cutting edge process node and advanced design methodology.
-Skilled in scripting language, such as Perl, C shell, TCL, Makefile, Python.
-Familiar with EDA tools like Innovus, ICC, Calibre, Tempus, PrimeTime, etc.
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence’s Intelligent System Design™ strategy, are essential for the world’s leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the world’s top 100 best-managed companies. Cadence solutions offer limitless opportunities—learn more at www.cadence.com.
