
Qualcomm India Private Limited
Engineering Group, Engineering Group > ASICS Engineering
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all.
SVE (System Validation & Emulation) team within Bangalore Design Center is responsible for validating hardware solutions and to integrate new hardware (IP cores and SoCs) to maximize software productivity and enable faster time to market. The validation organization is central to minimizing the number of chip turns in products, to the efficient transition of sound and reliable HW to SW organizations, and to the development of new validation methodologies. Validation team is currently looking for self-motivated engineers at all levels who will perform Hardware Security validation at core and system level, debug, in emulation and in post-Silicon.
As a Qualcomm Hardware Engineer within Hardware Security validation team, you will create functional validation test plan, develop validation test content, execute the test content on Pre-Silicon platform(FPGA based emulation platform), and Post-Silicon platform. You'll be responsible for debugging and triaging failures on both Pre-Si as well as Post-Si platform. You'll be working as an individual contributor and also lead junior engineers within the team. You'll will be expected to validate a portfolio of Hardware based Security IPs that manage Hardware based Security Encryption accelerators, SoC Security, Fuses, Access Control, Secure Boot and Trusted Platform Module. The role requires you to work with cross functional teams like Architecture, Product Engineers, Design, Design Verification, Software, Firmware, ATE/PTE, RMA/CE/CQE, and Program Managers. You would be expected to driver overall Security Hardware Validation on different segments of Qualcomm's business like Automotive, Mobile, Modem, Compute, and IOT/XR.
OR
Master's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
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