The Senior ASIC Hardware Verification Engineer is responsible for the end-to-end functional verification of complex digital designs (IP, Subsystem, or SoC). You will architect advanced UVM-based testbenches, define exhaustive verification plans, and lead the "coverage closure" process to ensure the design meets all architectural specifications before tape-out.
Verification Strategy: Define and document the verification plan (vPlan), including test scenarios, checkers, and functional coverage models.
Testbench Architecture: Architect and implement scalable, reusable verification environments using SystemVerilog and UVM
Advanced Stimulus: Develop constrained-random stimulus and directed tests to stress-test corner cases of the micro-architecture.
Debugging: Root-cause complex hardware failures by analyzing waveforms (VPD/FSDB) and collaborating with RTL designers.
Coverage Closure: Drive functional and code coverage to 100%, utilizing exclusions and refined stimulus to reach uncovered logic.
Performance & Power: Verify throughput, latency, and power-aware (UPF/CPF) features of the silicon.
Mixed-Methods: Integrate Formal Verification (JasperGold/VC Formal) for control logic and Hardware Emulation (Palladium/Zebu) for long-latency system tests.
Mentorship: Provide technical leadership to junior engineers and perform code reviews for testbench components.
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