Job Description

You will join our SDR R&D team as Senior Digital Hardware Engineer. Your primary technical focus will be the design, implementation, and verification of FPGA-based digital logic for SDR products. You will be involved in all aspects of the product development cycle, including concept, prototyping, design, development, testing, and manufacturing.

Digital engineers within our organization stand at the intersection of the many disciplines required to make new SDR products come to life, making this role critical to the team's success. Through your work you will have opportunities to further expand your skills and to participate in initiatives to grow the craft of digital design.

In This Role, Your Responsibilities Will Be:

• Collaborate with multi‑disciplinary hardware, firmware, and systems engineering teams to develop SDR products
• Own the full FPGA design, including logic implementation, data movement and analysis, testbenches, compilation, and timing analysis
• Develop register maps and generate documentation to ensure clear design intent to the broader project team
• Lead digital design by estimating efforts, providing updates on work status, and proactively identifying and addressing technical risks
  

Who You Are:

You partner with others to get work done. You can take a creative idea and put it into practice. You build and deliver solutions that meet customer expectations. You persist in accomplishing objectives despite obstacles and setbacks.

For This Role, You Will Need:

• Minimum Bachelor's degree in Electrical Engineering, Computer Science, Software Engineering, or related discipline
• Minimum 5 years of relevant engineering experience in digital hardware design
• Core FPGA / HDL
  • Proficiency in using VHDL and/or SystemVerilog to implement synthesizable logic targeting FPGAs
  • Experience in writing testbenches and simulation models to verify logic designs
  • Experience in designing and validating high-speed interfaces (i.e. DDR, PCIe, JESD204, Ethernet)
  • Experience with common clock domain crossing techniques and timing closure
• Development & Collaboration
  • Hands-on experience with bringing up prototype hardware and in defining and executing test plans to verify board level digital circuits
  • Exceptional problem-solving skills with the ability to analyze complex technical challenges
  • Proven ability to collaborate with cross‑disciplinary engineering teams and communicate technical concepts clearly in English to diverse stakeholders
    

Preferred Qualifications That Set You Apart:

• Static timing analysis and FPGA timing constraints
• Designing clocking architectures, including clock tree design, PLL configuration, and jitter analysis and mitigation techniques for high-speed digital systems
• Familiarity with Xilinx, Intel or Lattice FPGAs and CPLDs, and associated toolchains
• Scripting or programming languages (e.g., LabVIEW, Python) for hardware testing and automation
• Hands‑on experience using lab tools for FPGA bring‑up and debugging is a plus
• Hands-on experience with software defined radios

Our Culture & Commitment to You:At Emerson, we prioritize a workplace where every employee is valued, respected, and empowered to grow. We foster an environment that encourages innovation, collaboration, and diverse perspectives—because we know that great ideas come from great teams. Our commitment to ongoing career development and growing an inclusive culture ensures you have the support to thrive. Whether through mentorship, training, or leadership opportunities, we invest in your success so you can make a lasting impact. We believe diverse teams working together are key to driving growth and delivering business results.