Job Description

Position:

Senior Engineer (Level 2)- RTL Design

• Support SS/SoC RTL synthesis and constraints generation/validation, ensuring they meet performance, power, and area specifications
• Be the bridge between Backend and Frontend teams to reconcile on hand-off and timing issues
• Collaborate with cross-functional teams to not only resolve collateral issues but also to improve the overall PPA

Location Preference: Hyderabad

Experience: 4-6 yrs of work experience in owning RTL synthesis and constraints for complex IPs/SS/SoC

Duration of SOW 1 yr

Timeline to onboard Immediate (preferred) or 1 month notice

Location:

IN-KA-Bangalore, India (eInfochips)

Time Type:

Full time

Job Category:

Engineering Services