Job Description

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

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As a Senior Verification Engineer in the Secure Computing Products (SCG) Group at Microchip, the individual will be part of a larger digital logic design effort responsible for designing state-of-the-art hardware embedded controller solutions. This position requires someone comfortable will all aspects of Digital design development and is flexible enough to adapt to constantly evolving requirements. Must have good communication and organizational skills and work with multiple functional groups to create integrated solutions to satisfy embedded controller needs of various industries.

Job Responsibilities:

• Own the verification of complex blocks and subsystems within ARM-based SoCs.
• Able to perform digital design verification at the Block level, Chip level Functional verification.
• Define test plans from design specifications, implement constrained-random and directed tests, and drive coverage closure.
• Development of test environments using System Verilog and UVM verification methodologies.
• Integration with RTL and basic simulation bring-up for the design.
• Create multiple test cases as per test plan and launch regressions.
• Generate Code/Functional coverage, analyze coverage results and correlate with the test plan.
• Debug RTL and testbench issues, perform root cause analysis, and collaborate with design teams to resolve bugs.
• Contribute to AI/automation initiatives for regression management, coverage tracking, and debug automation.
• Work with architects and validation engineers to ensure end-to-end feature completeness and quality.
• Provide technical guidance and mentorship to junior engineers as required.
• Continuously improve verification methodology, reuse, and efficiency.

Requirements/Qualifications:

• Bachelor’s 7–9 years of experience in ASIC/SoC functional verification.
• or Master’s degree with 6 to 8 years in Electrical/Electronic Engineering or related field.
• Strong expertise in System Verilog and UVM methodology.
• Hands-on experience in developing block/subsystem/SoC-level verification environments.
• Solid understanding of AMBA,USB,I2C,SPI and eSPI protocols.
• Good understanding of Digital Design, RTL fundamentals, and simulation/debug flows.
• Familiarity with scripting (Python/TCL/Perl) for automation.
• Good programming skills with languages such as C, C++.
• Experience working with Cadence, Synopsys or Mentor verification platforms is an asset.
• Exposure to AI/ML-based verification, emulation, or acceleration is a plus.
• Excellent communication, teamwork, problem-solving abilities, strong analytical and debugging skills.
• Highly motivated, detail-oriented, and committed to delivering quality results.
• Ability to lead cross-site teams and manage complex design programs.

Travel Time:

0% - 25%

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