Job Description

Job Summary

We are looking for an experienced Standard Cell Layout Engineer to independently drive block-level layout design activities, ensuring high-quality execution and timely delivery. The role involves close collaboration with internal teams and customers, along with mentoring junior engineers and contributing to overall project management.

Key Responsibilities

Key Responsibilities

• Independently execute block-level layout design (Onsite/Offshore), including:
• Floorplanning as per area and top-level constraints
• Parasitic-aware routing
• Physical verification and sign-off
• Ensure on-time delivery of layouts with required quality standards
• Perform and debug physical verification checks (DRC, LVS, ERC, boundary conditions)
• Collaborate effectively with customers and cross-functional teams for successful project execution
• Guide and mentor junior team members, review their work and drive quality improvements
• Contribute to project planning, tracking, and execution efficiency

Skill Requirements

Required Skills (Must-Have)

• Strong understanding of CMOS and FinFET devices (characteristics, challenges, constraints)
• Good knowledge of digital circuit design (combinational & sequential circuits)
• Hands-on experience in:
• Standard Cell Layout Design (CMOS & FinFET)
• Physical verification flows (DRC, LVS, ERC, boundary checks) and debugging
• Expertise in:
• Floorplanning, routing, and verification of standard cell libraries
• EDA tools: Cadence Virtuoso XL, Calibre, PVS
• Proficient in Cadence Virtuoso layout editor and associated PV flow
• Good understanding of:
• Standard cell schematics
• Standard cell architectures
• Basic exposure to scripting (SKILL / Shell / Perl / Python)

Other Requirements

Desired Skills (Good-to-Have)

• Experience in advanced technology nodes (<16nm / FinFET nodes)
• Strong team collaboration and coordination skills across multiple teams
• Good written and verbal communication skills
• Positive attitude toward learning and adaptability

Education & Experience

• B.Tech / M.Tech in Electronics / VLSI / Related field with 3–10 years of industry experience

Keywords

Standard Cell Design, Layout Design, Physical Verification, Cadence Virtuoso XL, Calibre, Characterization, View Generation, CMOS, FinFET