Job Description

Job Summary

"Candidates with 2 to 4 years experience is mandatory

Experience in RTL coding using Verilog/SV

Experience in design using Xilinx or Altera devices

Experience in using Vivado or Quartus

Experience in supporting lab debug

Good understanding of FPGA debugging techniques

2 to 5 years experience in front end design

Experience in CDC/Linting/Tool Flow

Experience with ASIC/SoC development flow including synthesis/Timing Constraints development is preferred

Experience in RTL Synthesis

Scripting experience is preferable"

Key Responsibilities

1. To work closely with stakeholders to understand and refine design requirements.
2. To develop prototypes and proof-of-concept implementations to validate design decisions.
3. To mentor junior designers ,share knowledge and expertise through training sessions and documentation.
4. To collaborate with cross functional teams and other stakeholders to align software design with overall project goals.
5. To work with quality assurance teams to establish and maintain high-quality.

Skill Requirements

null

Other Requirements

null