Job Description

Job Summary

Perform end‑to‑end physical design flow:

Floorplanning

Power planning (PG grid, IR)

Placement & optimization

CTS (Clock Tree Synthesis)

Routing

Post‑route optimization

Achieve timing closure across all modes and corners

Resolve DRC, LVS, ERC and signoff violations

Handle low‑power design techniques:

Multi‑Vt, Multi‑voltage (UPF)

Power gating, clock gating

Perform physical verification and signoff:

STA (Primetime)

SI / Crosstalk

IR drop & EM analysis

Work on advanced nodes (7nm, 5nm, 3nm or below)

Collaborate with:

RTL & Micro‑architecture teams

DFT & Test engineers

Foundry and CAD teams

Debug complex timing, congestion, power, and variability issues

Drive methodology improvements and automation (scripts/flows)

Key Responsibilities

1. To work closely with stakeholders to understand and refine design requirements.
2. To develop prototypes and proof-of-concept implementations to validate design decisions.
3. To mentor junior designers ,share knowledge and expertise through training sessions and documentation.
4. To collaborate with cross functional teams and other stakeholders to align software design with overall project goals.
5. To work with quality assurance teams to establish and maintain high-quality.

Skill Requirements

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Other Requirements

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