Job Description

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience with hardware verification languages, design verification methodologies, and chip design flow.
• Experience with high-density micro-display technologies.
• Experience in developing and handling the UVM testbenches.

Preferred qualifications

• Master's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
• Experience with ultra-low latency, high-density micro-display technologies (e.g., MicroLED, Micro-OLED for Augmented Reality/Virtual Reality (AR/VR) XR systems).
• Experience transitioning UVM testbenches to hardware emulation platforms such as palladium or zebu.
• Familiarity with Python, Perl, and Makefile scripting for automated regression management.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will own the full verification life-cycle from verification planning and test execution to coverage closure, with an emphasis on meeting stringent AI/ML performance and accuracy goals, build constrained-random verification environments capable of exposing corner-case bugs and ensuring the reliability of Artificial Intelligence/Machine Learning (AI/ML) workloads on Tensor Processing Unit (TPU) hardware. You will collaborate closely with design and verification engineers in active projects and perform verification.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Define comprehensive verification strategies, test architectures, and detailed test plans covering full chip, subsystem, and block levels.
• Architect scalable SystemVerilog and Universal Verification Methodology (UVM) verification environments with constrained-random stimulus generation, protocol checkers, and automated scoreboards.
• Drive technical leadership across global verification teams, conducting rigorous test plan and verification code reviews.
• Partner with architecture and RTL design teams to resolve microarchitectural ambiguities, corner-case bugs, and specification updates.
• Establish bit-accurate reference models using C/C++ integrated via DPI-C to verify complex pixel-processing algorithms and video pipelines dynamically.