TalentLab

Senior Design Verification Engineer

TalentLab  •  Toronto, CA (Onsite)  •  2 months ago
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Job Description

Senior Design Verification Engineer

Our client is a key player in advancing digital technology by accelerating high-performance data communication—from AI and the metaverse to seamless video and beyond. Their technology is foundational to innovation across data-heavy industries such as data centers, AI, networking, storage, 5G, and autonomous vehicles. Known for their cutting-edge solutions and reliable execution, they help shape the future of digital systems.

The Digital Design Verification team fosters a collaborative, growth-oriented culture where engineers are encouraged to take on new challenges, learn continuously, and contribute to impactful projects. This group is dynamic, supportive, and a great fit for professionals looking to build their career in semiconductors.

What You’ll Do

  • Review design specifications and develop robust verification plans.

  • Build testbenches, run simulations, and debug failures to uncover design bugs.

  • Take initiative in leading, planning, and coordinating verification tasks with team members.

  • Create behavioral models of analog circuits.

  • Support bit-matching between RTL designs and MATLAB system models.

  • Integrate third-party VIPs for compliance testing of standard protocols.

  • Prepare design IP releases for customer delivery.

  • Collaborate in post-silicon validation and bring-up efforts.

  • Work closely with cross-functional teams—including Design, Systems, Analog, Firmware, and PD—to ensure final verification closure.

  • Continuously improve verification methodologies, tools, and team processes.

What You’ll Need

  • 3 to 8 years of relevant experience in design verification.

  • Strong skills in SystemVerilog and UVM for constrained-random verification.

  • Experience verifying SerDes PHYs, DSPs, and mixed-signal analog designs.

  • Knowledge of Ethernet and PCIe protocols is highly desirable.

  • Familiarity with formal verification and power-aware UPF verification techniques.

  • Proficiency in SystemVerilog, UVM, Python, Perl, C/C++, and GNU Make.


Please reach out to nick.weiszhaar@talentlab.com with your resume if you're a fit for the position and interested in learning more.

TalentLab

About TalentLab

Established in 1998, Talentlab delivers highly customized talent acquisition solutions for leading edge technology companies and places top technology stars in positions that precisely match their skills, aspirations and passions.

For more than a decade, we have successfully navigated the highs and lows of the technology industry. We've placed the brightest technology stars in highly specialized positions and helped manage and resolve complex strategic staffing challenges for some of the world's best technology companies.

We bring a seasoned team of experts to the table, a wealth of specialized industry knowledge and savvy, an extensive relational network and a robust infrastructure, all forged and refined in the trenches of real-world experience and success. Everything we do at Talentlab is fuelled with visionary passion and enthusiasm.

While we operate from a position of established success, our entrepreneurial spirit fuels our dedication to continually remain your most innovative, timely and dependable one-stop talent acquisition solution.

Industry
HR & Recruiting
Company Size
11-50 employees
Headquarters
Ottawa, CA
Year Founded
1998
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