Job Description

Job Summary

Open position 4

Exp :-- No particular number of years experience required once they meet the JD below , which implies a certain level of experience. Equally a person with 20 years experience doing power management is not useful as they cannot meet the mandatory parts of the JD.

Job description for the analog circuit verification role below

Mandatory

• Good communicator in English in written and verbal form
• Has some exposure, circuit design or analog verification, to serDes or clocking circuits at low or high data rates (minimum 1G)

o Serdes circuits

 Tx Output Driver, Tx serializer, Marching network, Termination circuits Rx CTLE, Rx DFE, RX deseilaizer Rx TISAR ADC, Piplelined ADC, Track and hold circuits passive and active,

o Clocking circuits

 PLL, DLL, ILO, Phase Interpolator, VCO (LC or Ring ), Charge Pump, PFD, TDC, PLL filter (integrating or proportional), prescalar, divider, clock buffering (CML or CMOS)

• Highly skilled in Cadence Virtuoso toolset and use of Spectre-X (Cadence), AFS (Siemens) and Solido PVTMC/HSV (Siemens) simulation tools
• Is strong at testbench creation given a circuit block spec
• Uses automated measurements using MDL and/or Ocean to check simulations and for reporting
• Good presentation skills in terms of generating and presenting simulation reports

Desirable

• Higher rates >10G on the above circuits
• Circuit porting skills

o Design tweaks and analog verification

Key Responsibilities

Open position 4

Exp :-- No particular number of years experience required once they meet the JD below , which implies a certain level of experience. Equally a person with 20 years experience doing power management is not useful as they cannot meet the mandatory parts of the JD.

Job description for the analog circuit verification role below

Mandatory

• Good communicator in English in written and verbal form
• Has some exposure, circuit design or analog verification, to serDes or clocking circuits at low or high data rates (minimum 1G)

o Serdes circuits

 Tx Output Driver, Tx serializer, Marching network, Termination circuits Rx CTLE, Rx DFE, RX deseilaizer Rx TISAR ADC, Piplelined ADC, Track and hold circuits passive and active,

o Clocking circuits

 PLL, DLL, ILO, Phase Interpolator, VCO (LC or Ring ), Charge Pump, PFD, TDC, PLL filter (integrating or proportional), prescalar, divider, clock buffering (CML or CMOS)

• Highly skilled in Cadence Virtuoso toolset and use of Spectre-X (Cadence), AFS (Siemens) and Solido PVTMC/HSV (Siemens) simulation tools
• Is strong at testbench creation given a circuit block spec
• Uses automated measurements using MDL and/or Ocean to check simulations and for reporting
• Good presentation skills in terms of generating and presenting simulation reports

Desirable

• Higher rates >10G on the above circuits
• Circuit porting skills

o Design tweaks and analog verification

Skill Requirements

Other Requirements