Job Description

Job Summary

Candidates with 5 to 7 years experience is mandatory

Good understanding of ASIC/SoC life cycle

Has participated in multiple ASIC/SoC verification till tapeout stage

Full chip TB Architecture definition Experience writing ASIC/SoC testplans

UVM based testbench development

1.Experience in ASIC/SoC Testbench definition

2.Experience to Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and the Universal Verification Methodology (UVM)."

SV functional coverage, Assertions coding

1.Expertise & hands-on experience in OVM/UVM methodologies using SV

2.Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans.

C based TB development

1. Experience in developing TB components for SOC with C, SV

Test case development, coding, execution, bug analysis

1. Experience in developing TB components, including functional coverage implementation and assertion coding
2. Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic.

3.Debug complex simulation failures using waveform viewer tools to isolate design bugs from testbench issues.

1. Experience in SOC C based tests coding & debugging

Key Responsibilities

Gate Level Simulation

Experience in Gate level simulation & netlist debugging

Regressions, coverage analysis

Experience in regression failure analysis

Functional and Code Coverage closure

participate in verification closure

Experience in Perl/Shell scriptin

Skill Requirements

Other Requirements